Senior/Lead/Staff Engineer – DFT

Experience:  3+ years to 10 years

Job Description:

• Experience in all phases of the DFT pre and post-Si for large SoCs -Implement DFT of SoC/Full-chip-level and/or high-speed cores/blocks
• Experience in high-speed, low-power, mixed-signal SoC’s is a plus
• Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries
• Experience in developing DFT architecture, Test-plan, implementation methodologies
• Experience in scan insertion, memory-BIST, JTAG/IJTAG, CTL, IEEE 1149.1/1500 wrappers, BSCAN, Compression, ATPG, Simulations, post-Si testing/debug